1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit and a method of controlling the semiconductor integrated circuit, particularly a semiconductor integrated circuit including a DLL circuit and a method of controlling the semiconductor integrated circuit.
2. Related Art
Generally, in a conventional semiconductor integrated circuit, a timing skew is generated between a clock signal transmitted from outside the circuit and a clock signal provided inside the circuit. Therefore, a circuit that accurately synchronizes data with a clock signal is required. A delay locked loop (hereafter, referred to as ‘DLL’) has been commonly used as a synchronization circuit. The DLL is a circuit that generates a locked internal clock signal by delaying an external clock signal.
A power down mode is often applied to a conventional semiconductor integrated circuit to reduce current consumption; however, internal circuits within such a semiconductor integrated circuit may operate unstably due to changes in voltage and internal temperature at the entry or end of the power down mode. Accordingly, the DLL receives an external clock signal even in the power down mode such that a DLL output clock signal is periodically updated even in the power down mode. When the frequency of the external clock signal is changed or not appropriately transmitted by the power down mode, wrong information from the external clock signal is updated in the DLL circuit, thereby causing errors in the operation of the inner circuits.